lhcb-trig L0 synchronisation issues
Let me just remind you the synchronisation task as it was defined:
Explain what is assumed for the FE synchronisation. How do you synchronise the FE data. How does your system deal with parts of your system (or the FE) having missed a clock, or suffers from single-event-upsets. How are these detected, how long to reset them, etc.. How is your system monitored/debugged.
I would like to discuss with you some initial (simple) assumptions. If we agree on them, they could be a base for further steps and comparisons.
1. L0 buffer is a clocked pipeline of FIXED latency (L=N*t), - t is a time unit equal 25 ns.
2. L0 trigger system as whole must have the same FIXED latency - from data coming to the L0 trigger system from the FE till the L0 decision arrives from TTC back to the FE.
3. The L0 trigger system is a composition of cables and electronics units. Each part has to have a FIXED latency (delay) defined as a number of time units (as seen from the L0 trigger system point of view).
4. Cables are analog delays - 5 ns/m or 5 m per time unit. - they must have their lenght as a multiplicity of 5 m, - otherwise an additional electronic analog delay must be used
5. Electronic units (processors, etc) have to be implementes as: - clocked pipelines (pipeline step is a time unit) - non-clocked units with fixed (in time units) propagation delay
6. Each electronic unit has to deliver its decison to the next unit of the L0 trigger system after FIXED latency (delay). - internal decision time may have a variable latency - internal decision time may not exceed the MAX FIXED latency - resynchronisation circuit (of variable latency) has to be added in order to to keep the total latency equal to MAX FIXED latency
7. FE data, flowing trough the L0 trigger system may (or must) be accompanied by the event tag in order to perform synchronisation error detection and data integrity check at different stages along the L0 trigger system
Please, comment on this.
Regards, Yuri Ermoline